1. Field of the Invention
The present invention generally relates to an NMOS driver circuit, and a method of fabricating an NMOS driver circuit with improved performance and reliability.
2. Description of the Related Art
An N-channel metal oxide semiconductor (NMOS) driver is known to have certain advantages as compared to conventional complementary oxide semiconductor (CMOS) drivers (e.g., such as P-channel field effect transistors (PFETs), N-channel field effect transistors (NFETs) and the like), such as smaller area, a switching performance gain, and less gate oxide stress.
The NMOS driver has a smaller area compared to a CMOS driver based on similar performance. Such a smaller area results from the CMOS device (e.g., PFETs, NFETs, etc.) having a design width which is double that of the NFET device because of a difference in hole and electron mobility. The mobility of electrons, which are the conducting carriers for NFETs, is about two times that of holes, which are the conducting carriers for PFETs. In order to switch a driver with similar rise and fall times, the width of a PFET device must be two times that of an NFET device.
Further, to reduce the cost of a typical dynamic random access memory (DRAM) circuit, single-workfunction gate materials (e.g., N+ polysilicon gate for both NFETS and PFETs) are used instead of dual-workfunction gate materials (e.g., N+ polysilicon for NFET and P+ polysilicon for PFET). Since a dual-workfunction-gate process requires extra mask steps and extra implant steps, it is generally more expensive than a single-work function-gate process. However, when the single-work function-gate process is used (e.g., N+ polysilicon gate only), the PFETs typically are buried channel PFETs, which have a substantially worse short-channel effect as compared with surface channel PFETs, or NFETs. For purposes of the present invention, the “short channel effect” is defined as the drop in device threshold voltage for a short-channel transistor when compared with that of a long-channel transistor. When the threshold voltage is below the designed target, excessive leakage current may occur even when the gate should supposedly be “OFF”.
Buried channel PFETs also tend to be more susceptible to the “punchthrough effect”. “Punchthrough” happens when the depletion region from the source and drain region of the transistor merge due to a high voltage applied on the drain terminal of the transistor. When punchthrough occurs, the drain current will no longer be controlled by the gate voltage. The loss of gate control can lead to circuit malfunction.
In order to avoid short channel effect and punchthrough effect in a buried channel PFET, the channel length of the nominal PFET used in the circuit is typically designed longer than that of NFET. This not only leads to circuit area penalty, but also to performance degradation.
Further, the size of a conventional CMOS driver is larger than that of an NMOS driver also because there is a minimum distance required between PFET and NFET devices for the conventional CMOS process. Good isolation between PFET and NFET requires optimum well design and latch up immunity. For example, a range of a typical distance between the PFET and NFET devices is about 150 nm to about 175 nm (e.g., the design rule or ground rule which is typically device-dependent and depends on the substrate's dopant level). The exclusive use of NFETs in the word line (WL) driver area reduces the circuit area by eliminating this minimum distance requirement since only p-wells exists.
Further, the conventional devices (CMOS devices such as PFETs and the like) require a killer switch for disabling wordline drivers that are activated but not selected by the row address. Since each one wordline is selected, any other wordlines that are activated must be disabled. For an NMOS wordline driver, however, no killer switch device is required since the charge on the non-selected wordlines can be discharged to ground via a pull-up or pull-down device. The size of the NMOS wordline driver circuit can therefore be further reduced.
For all of the reasons discussed above, a size reduction in chip area of about 1% for a 1 Gb DRAM can be obtained by using NMOS instead of CMOS in all wordline drivers.
Switching performance gains can also be realized by using NMOS drivers instead of CMOS drivers. The reasons are twofold: 1) electron mobility is higher than hole mobility. NFET devices operate faster than PFET devices, which leads to faster signal development during a data accessing operation; and 2) NFETs have far more superior turn-on (transient) characteristics than buried channel PFETs, since the subthreshold slope is degraded for buried channel PFETs. This is supported by circuit simulation. For example, as shown in FIG. 5, output waveforms are compared for the conventional CMOS wordline driver and the NMOS wordline driver. As shown, faster switching performance is demonstrated for the NMOS driver circuit.
Reliability of the NMOS drivers is greater than that of the conventional CMOS driver. One of the limitations for the highest boosted WL voltage Vpp is the reliability of the buried channel PFET used in the WL driver region. Due to the intrinsic work function difference between the gate and the drain, there is a built-in 1 V difference for the PFET gate and source/drain overlap region. Therefore, the off-state stress or the gate-induced drain leakage (GIDL) stress is much worse for the buried channel PFET than for the surface channel PFET, or NFET. The off-state stress occurs when there is a high field between the gate and the drain region. This high field can lead to impact ionization of either holes or electrons. Carriers with high enough energy can overcome the barrier at the gate oxide interface, travel towards the gate oxide, and cause permanent damage to the gate oxide interface. The additional 1V built-in potential at the gate and drain overlap region for buried channel PFET implies that the reliability of buried channel PFET is less superior than that of its surface channel counterpart or that of NFETs.
Further advantages of the NMOS driver over the CMOS driver are that less gate oxide stress occurs, and that the NMOS is more suited for negative WL low applications.
There have been attempts in the conventional methods and structures to implement an NMOS driver to resolve the problems inherent in using a CMOS driver. However, the NMOS driver devices also have some drawbacks.
For example, in a conventional NMOS driver as shown in FIG. 1B and as proposed by M. Nakamura, et al. (“A 20 Ns, 64M DRAM with Hierarchical Array Architecture”, IEEE J. of SSC, Vo. 32, No. 9, September 1996, p.1302), serious reliability problems develop related to junction breakdown on a boosted node, especially during a bum-in condition when a much higher voltage is applied (e.g., typically 1.5× that of the nominal operating voltage).
In the conventional technology (e.g., typical CMOS technology), the junction of the support devices can only sustain a voltage of up to 7V. Typically, during bum-in, the reverse bias voltage across the boost node junction is greater than 7V. As a result, damage may occur to the junction. That is, the reverse bias voltage may lead to junction breakdown and high leakage current between the junction and the substrate. In the conventional NMOS driver, this condition can result in permanent damage to the boost device, or at a minimum high junction leakage.
The consequence of such damage or leakage is that the boosted node voltage of the NMOS driver can no longer be sustained during wordline operation. This limitation is a main reason why an NMOS driver is not utilized in today's high performance and high density memory design.